9.6 A Wire-Delay Scalable Microprocessor Architecture for High Performance Systems

While microprocessor pipeline depths have increased dramatically over the last decade, they are fast approaching their optimal depth. As shown in Figure 9.6.1, the number of logic levels in modern processors is nearing 10 fanoutof-4 (FO4) inverter delay. Substantial further reductions will be undesirable due to pipeline overheads and power consumption [1]. Technology trends also show that global on-chip wire delays are growing significantly, eventually increasing cross-chip communication latencies to tens of cycles and rendering the expected chip area reachable in a single cycle to be less than 1% in a 35nm technology, as shown in Figure 9.6.2. The challenge for architects is to design new architectures that achieve both a fast clock rate (low FO4) and high concurrency, despite slow global wires. Because existing superscalar microarchitectures rely on global communication, they are poorly matched to the technology challenges of the coming decade.